1. Field of the Invention
The present invention relates to a semiconductor device for controlling electric power, and more specifically to a semiconductor comprising a thyrister and a bi-polar transistor, or an IGBT (Insulated Gate Bi-polar Transistor) and MOS (Metal-Oxide-Silicon), forming a half-bridge circuit structured vertically on one semiconductor chip.
2. Description of the Related Art
Conventionally, an H bridge circuit is used to control the clockwise/counterclockwise rotation of a motor. FIG. 1 shows a general view of an H bridge circuit. For example, a motor M operates in clockwise rotation when an electric current flows in the direction of arrow J.sub.1, while it operates in counterclockwise rotation when an electric current flows in the direction of arrow J.sub.2.
The H bridge circuit is formed by a plurality of semiconductor chips each comprising a transistor and being connected to others via lines.
In this case, a small-size apparatus can be realized if a plurality of transistors forming a half-bridge circuit, that is, a half of an H bridge, can be integrated into one semiconductor chip. At this time, it is optimal to form a half-bridge circuit with high-performance vertically-structured transistors in which an electric current flows through a semiconductor .substrate. However, it is very difficult to form a half-bridge circuit as one semiconductor chip because the transistors forming the upper and lower arms must be electrically separated from one another.
FIG. 2 shows a conventional commonly-used half-bridge circuit. FIG. 2A shows an example of the general configuration of the circuit, while FIG. 2B shows an equivalent circuit.
As shown in FIG. 2A, the conventional half-bridge circuit comprises a semiconductor chip 71 having a vertical type pnp transistor, a semiconductor chip 72 having a vertical type npn transistor, and a semiconductor chip 73 having a control IC, each being mounted on a substrate 74.
As shown in FIG. 2B, an output of the half-bridge is obtained at the connection point between the collector of the pnp transistor, that is, an upper arm, and the collector of the npn transistor, that is, a lower arm.
FIG. 3A shows a sectional view of the internal structure of the semiconductor device having a half-bridge circuit comprising two bi-polar transistors on one semiconductor chip. FIG. 3B shows an equivalent circuit.
As shown in FIG. 3A, an n.sup.- -type area 82 is formed on one area of an n.sup.+ -type semiconductor substrate 81, a p.sup.+ -type area 83 is formed on the n.sup.- -type area 82, and an n.sup.+ -type area 84 is formed on the p.sup.+ -type area 83.
On the other hand, an n.sup.- -type area 86 is formed on the other area of the n.sup.+ -type semiconductor substrate 81 and isolated from the n.sup.- -type area 82 by a p-type isolation area 85. p.sup.+ -type areas 87, 88, and 89, and an n.sup.+ -type area 90 are formed over the n.sup.- -type area 86.
The above described n.sup.+ -type area 81, the p.sup.+ -type area 83, and the n.sup.+ -type area 84 are respectively a collector area, a base area, and an emitter area of the vertically-structured npn transistor. A collector terminal C.sub.v is connected to the reverse surface of the n.sup.+ -type area 81, a base terminal B.sub.v is connected to the top surface of the p.sup.+ -type area 83, and an emitter terminal E.sub.v is connected to the top surface of the n.sup.+ -type area 84. A ground terminal T.sub.G is connected to the p-type isolation area 85 and to the emitter terminal E.sub.V, whereby the npn transistor is emitter-grounded.
The above described p.sup.+ -type areas 87 and 88, n.sup.+ -type area 90, and p.sup.+ -type area 89 respectively function as a collector area, a base area, and an emitter area of the horizontally structured pnp transistor. Additionally, a collector terminal C.sub.L is connected to the top surface of the p.sup.+ -type areas 87 and 88, a base terminal B.sub.L is connected to the top surface of the n.sup.+ -type area 90, and an emitter terminal E.sub.L is connected to the top surface of the p.sup.+ -type area 89. The collector terminal C.sub.v of the npn transistor is connected to the collector terminal C.sub.L of the pnp transistor, and a half-bridge output terminal T.sub.H is connected to the connection point.
In an equivalent circuit shown in FIG. 3B, the pnp transistor is an upper arm of a half-bridge circuit and formed as a horizontally structured element, and the npn transistor is a lower arm of a half-bridge circuit and formed as a vertically-structured element. Thus, a.sup.n output of the half-bridge is obtained through the terminal T.sub.H extended from the connection point of the collector terminals C.sub.V and C.sub.L.
As described above, when a half-bridge circuit is formed such that two transistors are connected to one semiconductor chip, the transistor of either the upper or the lower arm is a horizontally structured element. In the example shown in FIG. 3, the pnp transistor is an upper arm and a horizontally structured element.
In the thus structured semiconductor device, a control circuit (not shown in FIG. 3) can be conveniently integrated as a single semiconductor chip. However, there is a problem in that the size of the semiconductor chip becomes large depending on the size of the horizontally-structured transistor. Furthermore, a layer for electrically isolating a vertically-structured element from a horizontally structured element must be provided, which counteracts the realization of a smaller size semiconductor chip.
Generally, a horizontally structured transistor in which an electric current flows just beneath the surface of the semiconductor substrate is considerably inferior both in current amplification factor and current capacity to a vertically-structured transistor in which an electric current flows through the semiconductor substrate. Therefore, the performance of the entire semiconductor device comprising the above described half-bridge circuit is determined by an inferior horizontally structured element, resulting in performance reduction.. Accordingly, prior to the present invention effective merit cannot be expected from integrating a half-bridge circuit with two transistors on a single semiconductor chip.